Voltage Controlled DAR Envelope

Motivation

This is one more voltage controlled envelope generator in a series built around the Atmel AVR 328p and the MCP4921. Generates a delay/attack/release envelope on rising edge of gate. Retrigger possible during attack and release. Delay/attack/release time is manually and voltage controllable. Gate is polled every loop. CV input parameters are read with timer0 interrupt ISR (TIMER0_OVF_vect). Delay-, attack-, release- and EOC LED and outputs are switched. Software driven. The software is kept as simple as possible, so you can easily adapt it to your needs. Status signaled with LED. The attack and release timing is determined with tables, so you can easily adapt the timing to your needs as well.

Specs and features

• Delay, attack, release envelope
• All parameters voltage controlled
• Triggers at +3V
• Triggers at any waveform
• Software driven
• Buffered outputs
• Overvoltage protected inputs
• Status signaled by LED
• Status outputs
• Runs on +/-15V and +/-12V
• Power consumption around 35mA positive, 10mA negative rail

Implementation

Schematic

Description:

Top

Calibration

• None

Top

Building hints

• Don't forget to set the correct fuses for the Atmel AVR 328p

Special parts

• None

Download

Voltage Controlled DAR Envelope control board documentation download
Voltage Controlled DAR Envelope control board Gerber files download
Voltage Controlled DAR Envelope main board documentation download
Voltage Controlled DAR Envelope main board Gerber files download
Voltage Controlled DAR Envelope *.fpd file
Voltage Controlled DAR Envelope Software

The software is kept as simple as possible, so you can easily adapt it to your needs. The attack and decay timing is determined with tables, so you can easily adapt the timing to your needs as well.